1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to microcoded data processing systems having at least one processing unit capable of independent operation for which no activity (no-op) instructions are typically provided.
2. Description of the Related Art
For many data processing applications, the use of a general purpose data processing system does not permit efficient execution of specialized programs. To increase the efficiency of program execution, it has become common to develop, for incorporation in the central processing unit, specialized processing units, such as coprocessors for handling floating point and/or extended format arithmetic operations or, specialized processors with performance parameters optimized for manipulation of display information.
The activity of the specialized processor must be synchronized periodically with the activity of a general purpose microcoded central processing unit. However, the specialized processor can require more than one timing period for execution of the activity between the synchronization activity. Between the synchronization activity, the specialized processor executes procedures independently of the general purpose portion of the central processing unit. In the related art, a sequence of no-op (no operation or processor inactive) instructions are inserted in the instruction sequence to accommodate the period of time that the specialized processing unit is operating independently of the general purpose portion of the central processing unit. Typically, an instruction sequence (or instruction thread) is available for execution using general purpose portions of the central processing unit that are independent of the specialized processing unit. However, only a few (no-op) timing cycles are typically available for synchronization activities between the specialized processor and the general purpose central processing unit. The problem of how to integrate the plurality of instruction threads, where one of the threads must be executed in scattered groups of a few instructions, has eluded solution heretofore.
In the microcoded data processing system, one version of which is summarized by the block diagram of FIG. 1, an instruction 11 from a software program results in an address being entered in the program control register 12. The program control register 12 addresses a location in a memory unit 13 (typically a R(ead)O(nly)M(emory) unit. The signals from the addressed location are transferred to a microcode instruction register 14. The signals from the microcode instruction register 14 are applied to, and control, the apparatus performing the manipulation of data entities. The signals from the microcode instruction register 14 can determine the next instruction to be placed in the program control register, i.e., either from the software program instruction stream or from a predetermined (typically sequential) address in the memory unit 13. The implementation of a data processing system using microcode techniques has two advantages. First, the instruction set can be identical across a plurality of hardware implementations, the microcode circuitry serving as the interface mechanism. Second, complex sequences of activity can be initiated with a single software instruction, reducing the possibility of error in the formation of the software program.
The use of the microcoding techniques does not provide an obvious solution to the presence of sufficient apparatus in a central processing unit to execute independently two sequences of instructions. Indeed, the formal structure of the microcode sequences in the memory unit appear to provide a greater complication for independent execution of two instruction sequences even when one of the instruction sequences includes instructions referencing independently operating, specialized processors of the central processing unit and followed by no-op instructions with sufficient frequency to make the execution of a second instruction during the no-op instructions of the first instruction sequence attractive.
A need has therefore been felt for a technique that would permit simultaneous execution of two instruction sequences, in a central processing unit implemented with microcode techniques and having special purpose processing apparatus, without greatly increased complexity in the operation and with minimum additional apparatus.